This invention relates to vertical deflection circuits.
To provide vertical trace current to a vertical deflection winding, conventional vertical deflection circuits include, for example, two output transistors formed as a push-pull output stage. During vertical retrace, the current in the deflection winding is reversed in direction to be ready for the next trace interval. Typical deflection circuits may use a retrace capacitor coupled to the deflection winding to form a resonant retrace circuit for generating a resonant retrace current. A damping resistor coupled to the deflection winding damps any resonant oscillations of the deflection winding current after resonant retrace has been completed. It is desirable to design the vertical deflection circuit such that, during resonant retrace, the resonant retrace current is prevented from flowing in the output stage and in the damping circuit, thereby eliminating undesirable dissipation.